Miniaturized electronic components such as integrated circuits are typically manufactured using photolithography technology. In a photolithography process, a photoresist layer is deposited on a substrate, such as a silicon wafer. The substrate is baked to remove any solvent remained in the photoresist layer. The photoresist is then exposed through a photomask with a desired pattern to a source of actinic radiation. The radiation exposure causes a chemical reaction in the exposed areas of the photoresist and creates a latent image corresponding to the mask pattern in the photoresist layer. The photoresist is next developed in a developer solution to remove either the exposed portions of the photoresist for a positive photoresist or the unexposed portions of the photoresist for a negative photoresist. The patterned photoresist can then be used as a mask for subsequent fabrication processes on the substrate, such as deposition, etching, or ion implantation processes.
A major consideration in a photolithographic process is the depth of focus (DOF). DOF is a measurement of how much distance exists behind the lens of the exposure tool wherein the film plane still remains in focus. DOF is governed by the equationDOF=κ2λ/NA2 
where κ2 is a constant for a specific lithographic process, λ is the wavelength of the radiation used in the exposure, NA is the numerical aperture of the lens of the exposure tool. To improve the resolution of a photolithographic process, the semiconductor industry has continually moved to higher-NA exposure tools. However, the use of higher-NA tools tends to drastically decrease DOF, as indicated in the above equation.
In order to produce a lithographic pattern with high resolution, the exposure light must be focused throughout the photoresist film thickness and across the entire semiconductor wafer substrate. This requires that photoresist film thickness and the substrate topography are less than the DOF. However, for many semiconductor levels, especially the back-end-of-the-line (BEOL) levels, the substrate topography during exposure is often as large as, or even larger than, the available DOF. This would lead to greatly degraded lithographic results. The situation is further aggravated when a high-NA exposure tool is used, since the available DOF is small to begin with.
To alleviate the effects of substrate topography, various techniques have been used to planarize the surface of the substrate on which the photoresist is deposited. For example, underlayers or bottom anti-reflective coating (BARCs) have been spin-coated onto the substrate to planarize the substrate surface. However, spin-coated underlayers or BARCs only have short range (less than 2 μm) planarization effect. On the other hand, state of the art exposure systems are capable of compensating for topography, but only over a relatively long range (millimeters). Thus, there is a medium range of distances (from about 2 μm to about 500 μm) which are not planarized easily be spin coating techniques, and which are not compensated for by the exposure systems.
Another commonly used planarization technique is chemical-mechanical polishing (CMP). However, CMP is only capable of reducing substrate topography down to 100-200 nm ranges and performance can vary greatly from one circuit design to the next. Achieving predictable CMP performance can impose new constraints on design layouts and density.
Accordingly, it is desirable to provide a method which can planarize the substrate surface over a medium range of distances and which is suited for high-NA imaging processes.